The Design Process

Very few feats of engineering have ever been so on the first attempt. The following designs guided the project toward its successful conclusion.

Schematic Design Process

The CMOS Non-Inverting Oops Gate

Options were limited by the requirements that the buffer be non-inverting and exclusively contain CMOS technology. However, we wondered if a non-inverting CMOS buffer could be designed in a single stage. To try this, the NMOS and PMOS FETS were swapped. See Figure D1. We didn't expect it to work, but thought it worth examination.

Figure D1 - CMOS Non-Inverting Oops Gate Schematic

Consider Vin = 0V. Then Vgsn will never be greater than 0V, so the NMOS will turn off, yielding no pull-up path. Vsgp depends on the output. If the output is below -Vtp, then the PMOS is off, leaving the output unchanged at low voltage. However, if the output is above -Vtp, the PMOS turns on, creating a pull-down circuit, dropping the output to -Vtp. So far, this appears consistent with a non-inverting gate.

Now, consider Vin = Vdd. Vsgp will never exceed 0V, so the PMOS will turn off, yielding no pull-down path. Vgsn depends on the output. If the output is above Vdd-Vtn, the NMOS will turn off, eliminating the pullup circuit. If the output is below* Vdd-Vtn, the NMOS turns on, pulling the output to Vdd-Vtn. This indeed looks like a non-inverting gate. (*An opposite of the word "exceeds" does not exist, though there is current debate for "deceeds" to be added to the dictionary.)

A PSpice simulation revealed its VTC, in Figure D2. The gate does not invert the input, but the slope is unity near the output levels, meaning it provides no signal regeneration, yet if fed a square wave input, it would output the same square wave. The anomalous range in the middle may be problematic, depending on the load it was driving. Regardless, this design doesn't qualify as a candidate for this project.

Figure D2 - CMOS Non-Inverting Oops Gate Voltage Transfer Characteristic

The Series CMOS Inverters

Since the buffer must not invert its input, it must contain an even number of CMOS inverters. Since it contains at least one by mandate, it stands to reason that only one CMOS inverter must follow, in series. Any more than that would too dramatically affect the area component of the Figure of Merit. Thus, the non-inverting buffer schematic appears in Figure D3.

Figure D3 - CMOS Non-Inverting Buffer Schematic

The rest of the schematic design process need only produce the W/L ratios of each FET. Since the figure of merit prefers smaller, we chose the minimum feature size of 0.4um for the length of each FET, leaving the widths as the adjustable quantities. This buffer design was entered into the provided PSpice file and simulated. The transient response and average power consumption were plotted, yielding propagation delay and power consumption values. The Figure of Merit, as defined in the project specifications, was calculated, and used as a feedback indicator to guide alterations of the FET widths. After several iterations, we chose a final design. Refer to Appendix I: Dimension Design Iterations to see the progression.

In order to ensure the inverter acts properly, we chose to limit the propagation delay to 250 ps, which is 25% of the driving frequency. The rationale is that the signal can be correctly interpreted as long as it reaches half magnitude at half of its half-cycle. Without this limitation, the transistor size could have been decreased further, improving the figure of merit from 85461 to about 60000.

Some applications of a buffer require it to drive a load with high current. To supply this current, the second stage of FETS that interface with the load should have a high W/L ratio, but the FETS in the primary stage driving the secondary stage need only charge the gates, therefore can remain small. This fact was reflected in the final design. (See Figure D4, below.)

Layout Design Process 

On first attempt, a layout was constructed by adding the transistors, manually setting their size to the final schematic design dimensions, strategically positioning them, and connecting the traces. This yielded the layout in Figure D4.

Figure D4 - First Layout Attempt

This first layout attempt did not effectively utilize space, so we decided to break up MP2, the largest transistor, into two, making possible a more compact layout, which was the final layout design, shown in Figure D5 with the load inverter. This strategy reduced the required area by 30.6μm² (from 346.8 um^2 to 316.2 μm²), improving FOM2 by 8.8%

Figure D5 - Final Layout Design With Load Inverter