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CMOS Buffer Design & Layout Project

Group 5 - http://ee307w09-group05.pbwiki.com/ http://ee307w09-group05.pbwiki.com/f/EE307W09-05.jelib

James Boom: engineer.jboom_at_gmail.com

Daniel Kohler: dgkohler_at_calpoly.edu

Robert Peralta: rperalta_at_calpoly.edu

1 Introduction
2 Schematic Design
3 Layout Design
4 Schematic PSpice Code
5 Layout PSpice Code

Introduction

Non-inverting buffers serve to clean up noisy signals, provide delays to correct timing issues and interface small driver gates to large capacitive loads. Taking these considerations in to mind as well as the design specification outlined here, we designed, simulated and created a layout for a non-inverting CMOS buffer to drive a 1pF capacitor in parallel with the test inverter. Table I summarizes the overall performance of our final schematic and layout designs. We used a figure of merit defined in the design specifications for the schematic (FOM1) seen in (1) and the layout (FOM2) seen in (2) in order to compare the overall performance of the different designs.

FOM1 = (power dissipation in mW) x (propagation delay in ps) x (transitor area in μm²)	(1)
FOM2 = (power dissipation in mW) x (propagation delay in ps) x (cell area in μm²)	(2)

Table I: Figures of Merit for Buffer Designs

Design	Size (μm²)	Delay (ps)	Power (mW)	FOM (10^-26 J*m²)
Schematic	12.90	216.50	30.600	8550
Layout	312.8	232.93	32.133	234000

Table II: Transistor Sizes for Schematic and Layout Designs

Design	Dimension	NMOS1	PMOS1	NMOS2	PMOS2
Schematic	Width (μm)	2.75	5.50	8.00	16.00
	Length (μm)	0.40	0.40	0.40	0.40
Layout	Width (μm)	2.76	5.06	8.00	8.00/8.00
	Length (μm)	0.40	0.40	0.40	0.40/0.40

As seen in table I, FOM1 and FOM2 differed greatly even though they utilized similarly sized transistors, whose sizes appear in table II. This difference arises primarily because FOM1 does not take the minimum transistor and trace spacing into account, like FOM2 does. The layout design dissipates more power and creates a larger propagation delay because of parasitic resistances and capacitances, which are inherent to many, if not all, real world designs. [Parasitic resistances could increase the delay by reducing current, which would tend to reduce power consumption. The parasitic capacitances tend to increase delay and increase power dissipation.]

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Schematic Design

We optimized our schematic design, shown in fig. 1, by fixing the gate lengths to the minimum 0.4μm and sizing the gate widths to obtain the best (i.e. smallest) FOM1. After many iterations and reading the references provided on the project guidelines page, which can be found on the design process page, we arrived at transistor sizes, seen in Table II, which cause the PMOS transistors to "pull up" as much as the NMOS transistors "pull down," so that the propagation delays are fairly equal, i.e. the rise time of the buffer output approximately equals the fall time of the buffer output. We also made the first stage (P1 and N1) smaller, as it needs to provide less current to the second stage (P2 and N2), than the second stage needs to provide to the capacitor and inverter load, which attach to Vin of fig. 1.

Fig 1 Schematic with Transistor Sizes for the Optimized Schematic Design

To verify that the schematic design functioned as a non-inverting buffer, we used PSpice to simulate a voltage transfer characteristic (VTC) as shown in Figure 2. As the VTC shows, the 5V rail buffer has a reasonable switching threshold voltage of about 2.3V and switches from a Vol of 0V to a Voh of 5V. Both the switching threshold near 2.5V and rail-to-rail switching indicate that the schematic design of the buffer works well.

Fig 2 Optimized Buffer Voltage Transfer Characteristic. (VTC in green; Vsignal, in red, marks the switching threshold of the gate. Extremes of Voh = 5V and Vol = 0V span the voltage rails.)

To check that the schematic's noise margin met the design guideline's minimum noise margin of 0.5V, we used (3) with the critical voltages Vih and Vil found using the PSpice graph in Figure 3 and the extremes from Figure 2. The critical voltages occur when the absolute value of the slope of the VTC or dVsignal/dVin is greater than or equal to unity, as (4) expresses. Therefore, the noise margins appear in Table III.

NM = MIN(NMh, NMl)	(3)
NMh = Voh - Vih	(3a)
NMl = Vil - Vol	(3b)
\| dVinput / dVoutput \| >= 1	(4)

Fig 3 Graph of dVsingal/dVin for the optimized schematic in green. Using |dVsignal/dVin| = 1 as the criteria for the critical voltages, Vil = 2.3136V and Vih = 2.3775V

Table III: Noise Margins of Optimized Schematic

Voh (V)	5.000
Vih (V)	2.378	NMh (V)	2.622
Vil (V)	2.314
Vol (V)	0.000	NMl (V)	2.314 V

[The table above could use a caption and a number.]

These data confirm the integrity of the design. After verifying the design, we plotted the transient response in Figure 4 using PSpice under a 1GHz square wave stimulus, per design requirements. This timing data determined the buffer's propagtion delays in picoseconds, defined as the time delay between recieving a 50% input to reaching a 50% output. After finding the high to low and low to high delays we found the average propagation delay, which is found in Table I, with (5).

tpAVG = (tpLH + tpHL) / 2

(5)

Fig 4 Pspice generated transient analysis of schematic design with a 1Ghz input in red, the total system reponse in blue and the 50% mark in orange.

We estimated average power dissipation, the final component of FOM1, of our buffer-load system by running the PSpice simulation for 150 nanoseconds and averaging the extremely small fluctuations of the average power to get 30.678 mW as shown in fig. 5. The buffer, load inverter, load capacitor and parasitic capacitance of the buffer all contribute to the average power dissipation seen in fig. 5. The small fluctuations in the average power dissipation most likely arise due to the gate switching; if the system operates at a higher frequency, the fluctuations should diminish even further.

Fig 5 Power dissipation (in green) of buffer and load with a 1Ghz input to the circuit. The circuit reaches a near steady state power dissipation of 30.678mW by 150ns.

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Layout Design

We designed the layout using a program called Electric. It ensured that all aspects of the design stayed within conventional design rules. According to the specifications, the buffer (without load) must fit in a size no larger than a 102x85 unit cell, which is equivalent to 20.5x17µm². The cell has 3 unit (0.6 µm) power (Vdd) and ground lines running horizontally in the metal2 layer with 80 unit seperation, center to center. For a progressive commentary, the reader may refer to Design Process. Note that we broke up the second-stage PMOS into two parallel FETS to save space. See fig. 6 for the layout, and fig. 7 for the layout's schematic.

Fig 6 Layout of buffer design with its attached CMOS load. The buffer takes up an area of 18.6 μm x 17 μm, 30.6 μm² below the maximum allowed layout area for buffer.

Fig 7 Schematic for the layed out CMOS buffer. Note the two PMOS transistors in stage 2

After arriving at a final layout, we needed to calculate FOM2 using (2), which requires the total area of the buffer layout, the propagation delay of the buffer and load, and total system power dissipation. The buffer layout only spanned a length of 18.6μm, instead of the total given length of 20μm, which lowered our area value from 347μm to 316μm, a savings of 30.6μm, 8.8%. Electric exports a PSpice deck based on the layout, which we used to simulate the VTC seen in fig. 8, its derivative shown in fig. 9, the transient response shown in fig. 10, and the average power usage seen in fig. 11. The reader may download this project's Electric library here.

Fig 8 Voltage Transfer Characteristic (VTC) of the layed out buffer in green and

Vsignal in red to determine the switching threshold voltage where Vsignal = Vin.

Fig 9 In green the dVsignal/dVin curve for the layed out buffer going from magnitude zero to one. Using the |dVsignal/dVin| = 1 condition for the critical voltages, Vil = 2.1744V and Vih = 2.4499V

Before using PSpice to determine the speed and power of the buffer layout, we verified the noise margins by using the voltage transfer characteristic seen in fig. 9 and the process outlined in schematic section. Using fig. 10 we obtained the average propagation delay for the buffer as 232.93ps. From fig. 11 we read the average power dissipation for the buffer of 32.133mW.

Fig 10 Transient analysis in PSpice of the layed out buffer and load with the input in red, output in blue, and the 50% voltage point in orange. This timing information yielded the propagition delays used for FOM2.

Fig 11 Near steady state power dissipation, used in FOM2, in the layed out buffer-load circuit of 32.133mW.

After determining the size, propagation delay, and average power dissipation for the layout, we calculated FOM2 using (2). We then compared FOM1 and FOM2, both found in table I. FOM1 was considerably smaller primariliy because of the fact it did not take into account the required spacing between transistors and traces, like FOM2 did. The increased power and propagation delay in FOM2 arose because of the parasitic elements in the layout. Through the design process we found that theoretical designs like our schematic do not take into account real world design issues like spacing and parasitic elements; it is important to design and simulate applications using the most accurate parameters available as well as considering variables not represented in scematic level simulation.

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Schematic PSpice Code

*** Group 5 - http://ee307w09-group05.pbwiki.com/: James Boom, Daniel Kohler, Robert Peralta

*** SPICE deck for cell InvLoad{lay} from library EE307W09

*** Created on Sat Jan 03, 2009 14:44:17

*** Last revised on Mon Jan 05, 2009 00:25:00

*** Written on Tue Jan 13, 2009 22:36:44 by Electric VLSI Design System,

*version 8.08

*** Layout tech: mocmos, foundry MOSIS

*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF

*** P-Active: areacap=0.9FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq

*** N-Active: areacap=0.9FF/um^2, edgecap=0.0FF/um, res=3.0ohms/sq

***

*Polysilicon-1: areacap=0.1467FF/um^2, edgecap=0.0608FF/um, res=6.2ohms/sq

*** Polysilicon-2: areacap=1.0FF/um^2, edgecap=0.0FF/um, res=50.0ohms/sq

*** Transistor-Poly: areacap=0.09FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq

*** Poly-Cut: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.2ohms/sq

*** Active-Cut: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=2.5ohms/sq

*** Metal-1: areacap=0.1209FF/um^2, edgecap=0.1104FF/um, res=0.078ohms/sq

*** Via1: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=1.0ohms/sq

*** Metal-2: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq

*** Via2: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.9ohms/sq

*** Metal-3: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq

*** Via3: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq

*** Metal-4: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq

*** Via4: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq

*** Metal-5: areacap=0.0843FF/um^2, edgecap=0.0974FF/um, res=0.078ohms/sq

*** Via5: areacap=0.0FF/um^2, edgecap=0.0FF/um, res=0.8ohms/sq

*** Metal-6: areacap=0.0423FF/um^2, edgecap=0.1273FF/um, res=0.036ohms/sq

*.OPTIONS NOMOD NOPAGE

*** CELL: EE307W09:EmptyBuffer{lay}

.SUBCKT EmptyBuffer In Out gnd vdd

** Extracted Parasitic Capacitors ***

*Buffer transistors with width and length parameters

MN1 1 In gnd gnd CMOSN w=5.6u l=0.8u

MP1 1 In vdd vdd CMOSP w=5.5u l=0.4u

MN2 Out 1 gnd gnd CMOSN w=12u l=0.8u

MP2 Out 1 vdd vdd CMOSP w=10u l=0.4u

** Extracted Parasitic Resistors ***

.ENDS EmptyBuffer

*** CELL: EE307W09:InvLoad{lay}

.SUBCKT InvLoad In Out gnd vdd

Mnmos-10 gnd In_1nmos-10_n-trans-poly-left Out gnd CMOSN L=0.4U W=0.8U AS=1.4P

+AD=2.32P PS=5U PD=8.8U

Mpmos-5 Out In_2pmos-5_p-trans-poly-right vdd vdd CMOSP L=0.4U W=0.8U AS=2.9P

+AD=1.4P PS=11U PD=5U

** Extracted Parasitic Capacitors ***

C0 Out 0 3.667fF

C1 In 0 1.039fF

** Extracted Parasitic Resistors ***

R0 In_1nmos-10_n-trans-poly-left In_1nmos-10_n-trans-poly-left__0 9.3

R1 In_1nmos-10_n-trans-poly-left__0 In_1nmos-10_n-trans-poly-left__1 9.3

R2 In_1nmos-10_n-trans-poly-left__1 In_1nmos-10_n-trans-poly-left__2 9.3

R3 In_1nmos-10_n-trans-poly-left__2 In_1nmos-10_n-trans-poly-left__3 9.3

R4 In_1nmos-10_n-trans-poly-left__3 In 9.3

R5 In In__0 9.817

R6 In__0 In__1 9.817

R7 In__1 In__2 9.817

R8 In__2 In__3 9.817

R9 In__3 In__4 9.817

R10 In__4 In_2pmos-5_p-trans-poly-right 9.817

.ENDS InvLoad

** Extracted Parasitic Capacitors ***

C0 In 0 0.411fF

** Extracted Parasitic Resistors ***

*****************************************************************************

* *

* The above circuit file results after substituting *

* "_" for "#" *

* "-" for "@" *

* NMOS model "CMOSN" for "N" *

* PMOS model "CMOSP" for "P" *

* *

* In the TOP LEVEL CELL, substitute node "0" for "gnd" *

* *

* The above file also comments out the ".OPTIONS NOMOD NOPAGE" line *

* *

* Electric didn't produce the rest of the file *

*****************************************************************************

Vdd vdd 0 5V

Vin Signal 0 PULSE (0 5 0 5p 5p 495p 1n)

*** TOP LEVEL CELL: EmptyBufWLoad{lay}

XIn Signal In 0 vdd EmptyBuffer

XBufOut In Out 0 vdd InvLoad

Cout In 0 1pF

*.DC Vin 0 5 0.01

.TRAN 1p 10n 0 1p

.PROBE

.OP

*****************************************************************************

* FET Model Parameters *

* From http://www.mosis.org/Technical/Testdata/t14y_tsmc_025_level3.txt *

* TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring *

* DEV: N3740/10 * Temp= 27 *

*****************************************************************************

.MODEL CMOSN NMOS ( LEVEL = 3

+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.4317311

+ PHI = 0.7 VTO = 0.4 DELTA = 0

+ UO = 425.6466519 ETA = 0 THETA = 0.1754054

+ KP = 6.501048E-4 VMAX = 8.287851E4 KAPPA = 0.1686779

+ RSH = 4.062439E-3 NFS = 1E12 TPG = 1

+ XJ = 3E-7 LD = 3.162278E-11 WD = 1.232881E-8

+ CGDO = 6.2E-10 CGSO = 6.2E-10 CGBO = 1E-10

+ CJ = 1.81211E-3 PB = 0.5 MJ = 0.3282553

+ CJSW = 5.341337E-10 MJSW = 0.5 )

.MODEL CMOSP PMOS ( LEVEL = 3

+ TOX = 5.7E-9 NSUB = 1E17 GAMMA = 0.6348369

+ PHI = 0.7 VTO = -0.55 DELTA = 0

+ UO = 250 ETA = 0 THETA = 0.1573195

+ KP = 1.619415E-4 VMAX = 2.295325E5 KAPPA = 0.7448494

+ RSH = 30.0776952 NFS = 1E12 TPG = -1

+ XJ = 2E-7 LD = 9.968346E-13 WD = 5.475113E-9

+ CGDO = 6.66E-10 CGSO = 6.66E-10 CGBO = 1E-10

+ CJ = 1.893569E-3 PB = 0.9906013 MJ = 0.4664287

+ CJSW = 3.625544E-10 MJSW = 0.5 )

*****************************************************************************

.END

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Layout PSpice Code

* * * Group 5 - http://ee307w09-group05.pbwiki.com/: James Boom, Daniel Kohler, Robert Peralta

*** SPICE deck for cell BufWLoad{lay} from library EE307W09-05

*** Created on Fri Feb 20, 2009 14:06:01

*** Last revised on Fri Feb 20, 2009 14:27:21

*** Written on Wed Feb 25, 2009 15:16:42 by Electric VLSI Design System,